Tolerance Stack-Up Analysis Training (GD&T Application)

This 2 Days Course participants will be trained to apply tolerance stack-up analysis techniques to a wide variety of assemblies per GD&T requirements of ASME Y14.5M-1994 and ISO1101, from the very simple to the more complex situations commonly faced in industry today. Both plus and minus and geometrically toleranced assemblies will be examined and stack-up analysis taught and practiced on each. Many different datum structures will be discussed and analyzed. The concepts taught in this course are: loop analysis (also known as circuit diagrams), number charting, virtual condition, resultant condition, inner and outer boundaries, minimum airspace, maximum wall thickness, maximum interference, minimum and maximum overall dimensions, fixed and floating fastener assembly conditions, projected tolerance zones, the logic of stack-up analysis, statistical tolerancing , and much more.

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