Synopsys Workshop -System Verilog for Semiconductor Design and Verification Methodologies-PRAGYAN'26

Spots are filling fast – Register now and be part of this game-changing experience!

Deadline: 20th February 2026, 11:59 PM

Workshop Spotlight: System Verilog for Semiconductor Design and Verification Methodologies

For queries, Contact:

1. Swathi- 8825503167

2. Nithiyan- 7395825128

About the workshop:

SystemVerilog for Semiconductor Design and Verification Methodologies

This workshop introduces SystemVerilog fundamentals and its application in semiconductor design and verification. Participants will learn how SystemVerilog is used for writing synthesizable designs and building effective verification environments using industry-standard practices.

Perks and Insights:

Boost Your Resume & LinkedIn Profile – Receive a certificate from industry experts to strengthen your professional profile and unlock new career opportunities.

Exclusive Career Perks – Top 10 performers in the workshop get a direct interview opportunity with Synopsys for internships and full-time roles.

Unmatched Experience – Learn, network, and end the day with exclusive pro-shows and concerts to make your Pragyan’26 experience truly memorable.

Mandatory payments:

1. For entering the college - 250/-

2. Accommodation fee - 350/-

3. Caution Deposit - 300/- (if accommodation opted)